Clock recovery circuits and their associated frequency lock detection circuits are widely used, for example, in modern communications systems. Frequency lock detectors are used, for example, to obtain clock tolerance and offset information. Counter-based digital frequency lock detectors obtain clock offset information at fixed or programmable time intervals. Clock offset information is used in many applications, such as tuning clock generators. Typically, a counter-based digital frequency lock detector contains two equal-length counters. A first counter, generally referred to as the target counter, is clocked by the target clock. A second counter, generally referred to as the reference counter, is clocked by a reference clock.
The counter-based digital frequency lock detector ensures that the target clock stays within a desired tolerance of the reference clock. For example, a system, such as a SONET optical ring network, may require a clock offset tolerance of 100 parts-per-million (ppm). In such an implementation, both counters are initialized with the same initial count before starting to count. For example, if “up” counters are used, the initial count is set to zero. When the reference counter reaches a predefined count, such as 10,000, the value of the target counter is evaluated. If the target counter has a value between 9999 (−100 ppm) and 10001 (+100 ppm), the target clock has satisfied the 100 ppm offset requirement.
Thus, the output of the counter-based digital frequency lock detector is updated when the reference counter reaches the predefined count, and the target counter is examined to determine if the target counter value falls within a certain tolerance range. The tolerance range or offset range is an integer obtained by subtracting the maximum negative PPM count from the minimum positive PPM count. The predefined count is typically a very large number and the frequency offset cannot be determined until the reference counter reaches this large number. Thus, the frequency offset status output can only change at a fixed time interval, which may not be desirable in applications where prompt detection is required. A need therefore exists for a counter-based digital frequency lock detector that can evaluate a frequency offset more quickly than such conventional designs.